06-半加器

module half_adder
(
  input wire in_1,
  input wire in_2,
  output wire sum,
  output wire c_in
);  
  assign {c_in,sum}  = in_1 + in_2;
 
endmodule

`timescale 1ns/1ns
module tb_half_adder();
  reg in_1;
  reg in_2;
  wire　sum;
  wire　c_in;
  
  initial begin
    in_1 <= 1'b0；
    in_2 <= 1'b0；
  end
    
  initial begin
    $timeformat(-9,0,"ns",6);
    $monitor("@time:in_1 = %b,in_2=%b,sum=%b,count=%b",$time,in_1,in_2,sum,count);
  end
  
  always #10 in_1 = {$random} % 2;
  always #10 in_2 = {$random} % 2;
   
endmodule