10-阻塞赋值和非阻塞赋值

a = 1;
b = 2;
c = 3;
begin 
  a = b + 1; // a = 3
  b = a + 2; // b = 5
  c = a - 1; // c = 4
end

a = 1;
b = 2;
c = 3;
begin                         // 开始   结束
  a <= b + 1;  // 三条语句并行执行  3     3
  b <= a + 2;  //                 3     3
  c <= a - 1;  //                 0     0
end   

module blocking(
  input wire sys_clk,
  input wire sys_rst_n,
  input wire [1:0] in,
  output reg [1:0] out
);
  // 定义中间变量
  reg [1:0] in_reg;

  always@(posedge sys_clk or negedge sys_rst_n)
  begin
    if(sys_rst_n == 1'b0)
      begin
        in_reg = 2'b0;
        out = 1'b0;
      end
    else 
      begin
        in_reg = in;
        out = in_reg;
      end
  end
endmodule

`timescale 1ns/1ns
module tb_blocking();
  reg sys_clk;
  reg sys_rst_n;
  reg [1:0] in;
  wire [1:0] out;

  // 初始化时钟和复位信号,输入信号
  intial begin
    sys_clk = 1'b1;
    sys_rst_n <= 1'b0;
    in <=2'b0;
    #20;
    sys_rst_in = 1'b1;
  end
  
  // 模拟时钟
  initial begin
    #10;
    sys_clk = ~sys_clk;
  end  
  
  always #10 in <= {$random} % 4; // 生成非负数0,1,2,3

  blocking block_inst(
     .sys_clk (sys_clk),
     .sys_rst_n (sys_rst_n),
     .in      (in),
     .out     (out)
  );
    
endmodule

module nonblocking(
  input wire sys_clk,
  input wire sys_rst_n,
  input wire [1:0] in,
  output reg [1:0] out
);
  // 定义中间变量
  reg [1:0] in_reg;

  always@(posedge sys_clk or negedge sys_rst_n)
  begin
    if(sys_rst_n == 1'b0)
      begin
        in_reg <= 2'b0;
        out <= 1'b0;
      end
    else 
      begin
        in_reg <= in;
        out <= in_reg;
      end
  end
endmodule